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APA3541/4
Class AB Stereo Headphone Driver with Mute
Features
* * * * * * * * * * *
High Signal-to-Noise Ratio High Slew Rate Low Distortion Large Output Voltage Swing Flexible Mute Function Excellent Power Supply Ripple Rejection Low Power Consumption Short-circuit Elimination Wide Temperature Range No Switch ON/OFF Clicks Integrated Voltage Divider (VDD/2) to Eliminate External Resistors
Applications
*
Portable Digital Audio
General Description
The APA3541/4 is an integrated class AB stereo headphone driver contained in an SO-8 or a DIP-8 plastic package with Mute feature . Besides the common Mute feature , the APA3541/4 further integrates a voltage divider inside the chip . Thus , the external resistors can be eliminated . The APA3541 has a fixed gain of 0dB and the APA3544 has a fixed gain of 6dB so that external gain setting is unnecessary. The device is fabricated in a CMOS process and has been primarily developed for portable digital audio applications .
Ordering and Marking Information
A P A 3 5 4 1 /4
H a nd lin g C o d e T em p. R ange P a ck a g e C o d e P ackage C ode J : P D IP - 8 Y : C h ip F ro m T em p. R ange I : - 4 0 to 8 5 C H a n d lin g C o d e TU : Tube
K : SOP - 8
TR : Tape & Reel
A P A 3 5 4 1 /4 J :
A P A 3 5 4 1 /4 XXXXX
X X X X X - D a te C o d e
A P A 3 5 4 1 /4 K :
A P A 3 5 4 1 /4 XXXXX
X X X X X - D a te C o d e
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. B.1 - Apr., 2003 1 www.anpec.com.tw
APA3541/4
Block Diagram
M UTE
O ut A
1 0dB (6dB ) 0dB (6dB )
8
V DD
M ute
2
A +
B +
7
O ut B
Input A
3 180k ( 90k ) 180k ( 90k )
B IAS
6
BIAS
V SS
4
5
Input B
* The values in parenthessis are for the APA3544.
Function Pin Description
Pin Name Out A Mute Input A VSS Input B BIAS OUT B VDD I/O O I I I I O Function Description A channel output pin Chip disable control input, low active and high for normal operating A channel input terminal Power ground pin B channel input terminal Right channel bias input pin B channel output pin Power input pin
Absolute Maximum Ratings
Symbol VDD tSC(O) TA TJ TSTG TS VESD Parameter Supply Voltage Output Short-circuit Duration, at TA=25C, Ptot=1W Operating Ambient Temperature range Maximum Junction Temperature Storage Temperature Range Soldering Temperature,10 seconds Electrostatic Discharge Rating 7 20 -40 to 85 150 -65 to +150 300 -3000 to 3000
*1
Unit V S C C C C V
Note: 1. Human body model : C=100pF, R=1500, 3 positive pulses plus 3 negative pulses
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APA3541/4
Thermal Characteristics
Symbol RTHJA Parameter Thermal Resistance from Junction to Ambient in Free Air DIP-8 SOP-8 Thermal Resistance from Junction to Case DIP-8 SOP-8 Rating 108 210 45 40 Unit K/W
RTHJC
K/W
Electrical Characteristics
VIN=0dBV, VCC=5V, TA=25C, f=1kHz, RL=32 (unless otherwise noted)
APM3541/4 Symbol VDD IQ Imute VTM GVCL Parameter Supply Voltage Quiescent Current Mute Current Mute Terminal Voltage Differential Channel Voltage Gain Vin=1Vrms,f= 1kHz,RL=32 GVCL Voltage Gain Vin=0.5Vrms, f=1kHz,Rl=32 APA3544 THD Total Harmonic Channel Distortion Factor PU1 Rated Output Power1 BW<80kHz RL=32,THD+N=0.1%,BW<8 APA3541 0kHz APA3544 50 75 105 140 4 6 0.03 55 80 110 mW 145 -93 APA3541 Channel Separation Mute Attenuation Ripple Rejection F=1kHz APA3544 ATT RR VIN=1Vrms,f=1kHz,Mute=L FRR=100Hz,VRR=-20dBV -65 65 50 -70 70 60 dB dB -90 -95 dB -85 dBV 8 0.1 % APA3541 0.3 -0.5 -2 VIN= 0 Vrms Test Condition Unit
Min. Typ. Max.
3.0 5.0 3.5 200 0.7 0 0 1.6 0.5 2 dB 6.0 5 V mA A V dB
mW
PU2 VNO CS
Rated Output Power2 Output Noise Voltage
RL=16,THD+N=0.1%,BW<8 APA3541 0kHz BW=20~20kHz , Vin=0Vrms APA3544
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APA3541/4
Test and Application Circuit
1 F V IN B
10F
220 F
Input B 5
B IAS 6
O ut B 7
VDD 8 100 F
V DD
B IAS 0dB(6dB) A PA 3541 (A PA 3544)
+ +
B
0dB(6dB) A
M UT E
4 V SS Input A
3 M ute
2 O ut A
1 220 F
1 F V IN A 1 F
100k V MU TE H : S peaker Action L : M ute on
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APA3541/4
Typical Characteristics
8 7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7 5
RL=32
RL=32
Quiescent Current : IQ (mA)
Bias DC Voltage :Vbias (V)
4
MUTE : OFF
3
2
1
MUTE : ON
0 0 1 2 3 4 5 6 7
Figure 1 : Supply Voltage : VDD (V)
Figure 2 : Supply Voltage : VDD (V)
10 0
+8 +6
APA3541 VDD=5V VIN=0dBv
Output Voltage : VOUT (dBV)
Voltage Gain : GVC (dB)
0.8 1.2 1.6 2
-10 -20 -30 -40 -50 -60 -70 -80 0
VDD=5V VIN=0dBv f =1 kHz RL=32
+4 +2 +0 -2 -4 -6 -8 -10
0.4
-12 10
100
1k
10k
100k
Figure 3 : Mute Control Voltage : VTM (V)
Figure 4 : Frequency :f (Hz)
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APA3541/4
Typical Characteristics Cont.
10
10
Total Harmonic Distortion : THD+N (%)
Total Harmonic Distortion : THD+N
5 2 1 0.5 0.2
VDD= 5V RL=32 BW< 80kHz
5 2 1 0.5
VDD= 3V RL=32 BW< 80kHz
(%)
0.2 0.1
f =10KHz
f =10kHz
0.1
0.05 0.02 0.01 -40
0.05 0.02 0.01 -40
f =1KHz , 100Hz
f =1kHz , 100Hz
-30 -20 -10 +0 +10
-30
-20
-10
+0
+10
Figure 5 : Output Voltage : VOUT (dBv)
Figure 6 : Output Voltage : VOUT (dBv)
Total Harmonic Distortion : THD+N (%)
Total Harmonic Distortion : THD+N (%)
10 5 2 1 0.5
10 5 2 1 0.5
VDD= 5V RL=16 BW< 80kHz
VDD= 3V RL=16 BW< 80kHz
f =10kHz
0.2 0.1 0.05 0.02 0.01 -40 -30 -20 -10 +0 +10
f =10kHz
0.2 0.1 0.05 0.02 0.01 -40 -30 -20 -10 +0 +10
f =1kHz , 100Hz
f =1kHz , 100Hz
Figure 7 : Output Voltage : VOUT (dBv)
Figure 8 : Output Voltage : VOUT (dBv)
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APA3541/4
Typical Characteristics Cont.
+0
+0
VDD=5V
-10
Channel Separation : CS (dB)
VDD=5V VIN=0dBv RL=32
Mute Attenuationt : ATT(dB)
1k 10k 100k
-20 -40 -60 -80 -100 -120 10
RL=32
-20 -30 -40 -50 -60 -70 -80 -90 100 10
100
50 100
1k
10k
100k
Figure 9 : Frequency :f (Hz)
Figure 10 : Frequency :f (Hz)
0 -1 0
fRR=100Hz VRR=-20dBv
Ripple Rejection : RR (dB)
-2 0 -3 0 -4 0 -5 0 -6 0 -7 0 -8 0 -9 0 -1 0 0
0
1
2
3
4
5
6
7
Figure 11 : Supply Voltage : VDD (V)
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APA3541/4
Application Note
Input Capacitor , Ci In the typical application an input capacitor , Ci , is required to allow the amplifier to bias the input signal to the proper DC level for optimum operation . In this case , the external capacitor Ci and the internal resistance Ri form a high-pass filter with the corner frequency determined in the follow equation: fc (highpass)= 1/ (2RiCi) (1) The value of Ci is important to consider as it directly affects the low frequency performance of the circuit. Consider the APA3541 where Ri is 180k and APA3544 is 90k internal fixed . Equation is reconfigured as follow: Ci= 1/(2*180k*fc) for APA3541 Ci= 1/(2*90k*fc) for APA3544 And the ceramic capacitor is recommanded. Bias Capacitor , Cb As with any power amplifier , proper supply bypassing is critical for low noise performance and high power supply rejection . The capacitor location on both the bypass and power supply pins should be as close to the device as possible . The effect of a larger half supply bias capacitor is improved PSRR due to increased half-supply stability . Typical applications employ a 5V regulator with 10F and a 0 . 1F bias capacitors which aid in supply filtering . This does not eliminate the need for bypassing the supply nodes of the APA3541/4 . The selection of bias capacitors , especially Cb , is thus dependent upon desired PSRR requirements , click and pop performance . The capacitor is fed from a 95k source inside the amplifier . To keep the start-up pop as low as possible , the relationship shown in equation should be maintained . 1/(Cb*95k) 1/{Ci*Ri} (3) As an example , consider a circuit where Cb is 4.7F, Ci is 1F and APA3541 Ri is 180k . Inserting these values into the equation we get 2.24 5.55 which satisfies the rule . Bias capacitor , Cb , values of 2.2F to 10F ceramic or tantalum low-ESR capacitors are recommended for the best THD and noise performance . Output Coupling Capacitor, Cc In the typical single-supply SE configuration , an output coupling capacitor (Cc) is required to block the DC bias at the output of the amplifier thus preventing DC currents in the load . As with the input coupling capacitor , the output coupling capacitor and impedance of the load form a high-pass filter governed by equation . fc(highpass)= 1/(2RLCc) (4) For example , a 220F capacitor with an 32 speaker would attenuate low frequencies below 22Hz . The main disadvantage , from a performance standpoint , is the load impedance is typically small , which drives the low-frequency corner higher degrading the bass response . Large values of Cc are required to pass low frequencies into the load . Optimizing Depop Circuitry When the amplifier is in mute mode , both of the output stage and input bypass continues to be biased . And no pop noise will be heard during the transition out of mute mode . Power Supply Decoupling, Cs APA3541/4 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to ensure the output total harmonic distortion (THD) is as low as possible . Power supply decoupling also prevents the oscillations causing by long lead length between the amplifier and the speaker . The optimum decoupling is achieved by using two different type capacitors that target on different type of noise on the power supply leads . For higher frequency transients , spikes , or digital hash on the line , a good low equivalent-series-resistance (ESR) ceramic capacitor, typically 0.1F placed as close as possible to the device V lead works best . For filtering lowerDD frequency noise signals , a large aluminum electrolytic capacitor of 10F or greater placed near the audio power amplifier is recommended .
(2)
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APA3541/4
Packaging Information
PDIP-8 pin ( Reference JEDEC Registration MS-001)
D
E1 1
E
A L e2 e1 e3 A1
A2
1 E3
Dim Min. A A1 A2 D e1 e2 e3 E E1 E3 L 1 0.38 2.92 9.02
Millimeters Max. 5.33 3.68 10.16 2.54BSC 0.36 1.14 7.62 BSC 6.10 2.92 15 7.11 10.92 3.81 0.240 0.115 0.56 1.78 0.014 0.045 Min. 0.015 0.115 0.355
Inches Max. 0.210 0.145 0.400 0.100BSC 0.022 0.070 0.300 BSC 0.280 0.430 0.150 15
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APA3541/4
Packaging Information
SOP-8 pin ( Reference JEDEC Registration MS-012)
E
H
e1 D
e2
A1
A
1 L
0.004max.
Dim A A1 D E H L e1 e2 1
Mi ll im et er s Min . 1. 35 0. 10 4. 80 3. 80 5. 80 0. 40 0. 33 1. 27B S C 8 Max . 1. 75 0. 25 5. 00 4. 00 6. 20 1. 27 0. 51 Min. 0. 053 0. 004 0. 189 0. 150 0. 228 0. 016 0. 013
0.015X45
Inche s Max . 0. 069 0. 010 0. 197 0. 157 0. 244 0. 050 0. 020 0. 50B S C 8
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APA3541/4
Physical Specifications
Terminal Material Lead Solderability Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb) Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3.
Reflow Condition
(IR/Convection or VPR Reflow)
Reference JEDEC Standard J-STD-020A APRIL 1999
temperature
Peak temperature
183C Pre-heat temperature
Time
Classification Reflow Profiles
Convection or IR/ Convection Average ramp-up rate(183C to Peak) 3C/second max. 120 seconds max Preheat temperature 125 25C) 60 - 150 seconds Temperature maintained above 183C Time within 5C of actual peak temperature 10 -20 seconds Peak temperature range 220 +5/-0C or 235 +5/-0C Ramp-down rate 6 C /second max. 6 minutes max. Time 25C to peak temperature VPR 10 C /second max.
60 seconds 215-219C or 235 +5/-0C 10 C /second max.
Package Reflow Conditions
pkg. thickness 2.5mm and all bgas Convection 220 +5/-0 C VPR 215-219 C IR/Convection 220 +5/-0 C pkg. thickness < 2.5mm and pkg. volume 350 mm pkg. thickness < 2.5mm and pkg. volume < 350mm Convection 235 +5/-0 C VPR 235 +5/-0 C IR/Convection 235 +5/-0 C
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APA3541/4
Reliability test Program
Test item SOLDERABILITY HOLT PCT TST ESD Latch-Up Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B, A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD 78 Description 245 C , 5 SEC 1000 Hrs Bias @ 125 C 168 Hrs, 100 % RH , 121 C -65 C ~ 150 C , 200 Cycles VHBM > 2KV, VMM > 200V 10ms , Itr > 100mA
Carrier Tape & Reel Dimensions
t E Po P P1 D
F W
Bo
Ao
D1
Ko
T2
J C A B
T1
Application
A 330 1
B 62 +1.5 D
C 12.75+ 0.15 D1
J 2 0.5 Po 4.0 0.1
T1 12.4 0.2 P1 2.0 0.1
T2 2 0.2 Ao 6.4 0.1
W 12 0. 3 Bo 5.2 0. 1
P 8 0.1 Ko 2.1 0.1
E 1.750.1 t 0.30.013
SOP- 8
F 5.5 1
1.55 +0.1 1.55+ 0.25
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APA3541/4
Cover Tape Dimensions
Application SOP- 8 Carrier Width 12 Cover Tape Width 9.3 Devices Per Reel 2500
Customer Service
Anpec Electronics Corp. Head Office : 5F, No. 2 Li-Hsin Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 7F, No. 137, Lane 235, Pac Chiao Rd., Hsin Tien City, Taipei Hsien, Taiwan, R. O. C. Tel : 886-2-89191368 Fax : 886-2-89191369
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